30 nm In0.7Ga0.3As Inverted-Type HEMTs with Reduced Gate Leakage Current for Logic Applications

We have fabricated 30 nm In0.7Ga0.3As Inverted-Type HEMTs with outstanding logic performance, scalability and high frequency characteristics. The motivation for this work is the demonstration of reduced gate leakage current in the Inverted HEMT structure. The fabricated devices show excellent Lg scalability down to 30 nm. Lg = 30 nm devices have been fabricated with exhibit gm = 1.27 mS/μm, S = 83 mV/dec, DIBL = 118 mV/V, ION/IOFF = 4 x 10, all at 0.5 V. More significantly, the removal of dopants from the barrier suppresses forward gate leakage current by over 100X when compared with equivalent normal HEMTs. The Lg = 30 nm devices also feature record high-frequency characteristics for an inverted-type HEMT design with fT = 500 GHz and fmax = 550 GHz. Introduction As conventional Si CMOS scaling approaches the end of the roadmap, III-V based FETs appear as an increasingly viable alternative to continue transistor size scaling [1-2]. A great deal of the excitement about the prospects of III-Vs comes from the excellent logic characteristics that have recently been demonstrated in InGaAs HEMTs with gate lengths as small as 30 nm [3]. While being quite far in structure from an ideal logic III-V MOSFET, the HEMT has demonstrated to be an excellent model system to study fundamental device physics and technology issues and to provide well calibrated and relatively parasitic-free device results to support the development of simulators that would allows us to chart the future of a III-V logic technology [4]. In this regard, there is great value in continuing to push the scaling of HEMTs so as to explore significant device physics issues in the relevant dimensional range. It is well known that lateral scaling demands harmonious vertical scaling. Reduction of insulator thickness results in greatly increased gate leakage current [5]. This is what currently limits the reduction in HEMT lateral dimensions. Suppressing this, would allow us to scale the HEMT below 30 nm while preserving excellent logic characteristics. In this work, we demonstrated an inverted-type HEMT design that mitigates forward gate leakage current by over two orders of magnitude and yields excellent logic characteristics. This device architecture is also directly amenable to the incorporation of a high-K gate dielectric in the gate stack which should allow much further scaling. Process Technology Fig. 1 shows a cross section of epitaxial layer structure used in this work and a schematic of the fabricated device structure. Our device features an InAlAs/InGaAs double-heterostructure design where the upper Si-doping is located further away from the channel than in conventional designs (8 nm vs. about 3 nm). As a result, after a triple recess process [5], the dopant layer is eliminated in the intrinsic device resulting in a dopantfree InAlAs barrier. This gives rise to a conduction band shape for the barrier that, for the same sheet carrier concentration, is more rectangular than in the conventional design, as shown in Fig. 2. This should significantly suppress gate leakage current, especially in the forward gate bias regime. Device fabrication follows closely our previous device demonstrations [6]. We use a three-step recess process that yields a barrier thickness in the intrinsic region, tins, of about 4 nm. In this work, we have devices with Lg values in the range of 30 to 130 nm. Fig. 3 shows STEM images of a fabricated 30 nm device. The side-recess-length (Lside) was set at 80 nm. Fig. 1 Heterostructure and schematic of InGaAs Inverted HEMT. It features delta-doping in the top InAlAs layer that is etched away in the intrinsic device DC and Logic Characteristics Fig. 4 shows output characteristics of an inverted HEMT with Lg of 30 nm. The device exhibits excellent pinch-off and saturation characteristics. Fig. 5 shows the subtreshold and gate current characteristics of a 30 nm I-HEMT against those of a previously demonstrated normal In0.7Ga0.3As HEMT with a similar channel design, barrier thickness (4 nm), gate length, and Lside value. The inverted HEMT displays comparable subthreshold characteristics to the normal HEMT with a subthreshold swing of 83 mV/dec and DIBL of 118 mV/V at VDS = 0.5 V. Remarkably, the inverted HEMT exhibits much lower values of OFF-state current and gate leakage current, especially in the forward regime where a reduction of over 100X is achieved. 0 10 20 30 40 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Elctron dnsity [x 10 18 cm 3 ] C B P ro fil es [e V] Vertical depth [nm] Inverted HEMT Normal HEMT VGS=+0.22V for I-HEMT VGS=+0.25V for N-HEMT 0.0 0.5 1.0 1.5 2.0 Fig. 6 shows subthreshold characteristics for devices with Lg from 130 nm down to 30 nm at VDS = 0.5 V, together with gate leakage current (IG). The devices show harmonious scaling with very small VT roll off in this dimensional range. Fig. 2 Self-consistent Schrodinger-Poisson calculation of conduction band profile and electron density in Inverted HEMT and conventional HEMT at the same ns = 1.3 x 10/cm. Fig. 3 Cross-section STEM images of inverted HEMT with LG = 30 nm. The barrier thickness, tins is estimated to be 4 nm. [TEM analysis was carried out at NCNT and UNIST in Korea.] Fig. 4 Output characteristics of 30 nm InGaAs Inverted HEMT. Fig. 5 Subthreshold and IG characteristics of 30 nm InGaAs Inverted HEMT and normal HEMT. Off-state ID and IG characteristics are greatly suppressed in Inverted HEMT because of the rectangular shape of the barrier. Fig. 7 shows ION, IOFF and corresponding ION/IOFF ratio as a function of Lg for both types of devices at VDS = 0.5 V [7]. The inverted HEMT shows much lower values of IOFF, and a significantly higher ION/IOFF ratio across the entire dimensional rage when compared with the rectangular HEMT. At Lg=30 nm, the ION/IOFF ratio is ~ 4 x 10. A trade-off of the inverted design is also evident in this figure. ION for the inverted HEMTs is slightly lower than for normal HEMTs. This comes from an increase in source resistance (Rs) which is a consequence of a reduction of the sheet carrier concentration in the extrinsic portion of the device as a result of having the upper Si-doping plane further away from the channel. This can be more quantitatively observed in Fig. 8 which graphs the resistance measured though the gate-current 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 VGS=-0.2V VGS=-0.1V VGS=0V VGS=0.1V VGS=0.2V VGS=0.3V